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KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
KS0078 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
* Character type dot matrix LCD driver & controller * Internal driver : 34 common and 120 segment signal output * Easy interface with 4-bit or 8-bit MPU * Clock synchronized serial Interface * 5 x 8 dot matrix possible * 6 x 8 dot matrix possible * Bi-directional shift function * All character reverse display * Display shift per line * Voltage converter for LCD drive voltage : 13 V max (2 times / 3 times) * Various instruction functions * Automatic power on reset
FEATURES
* Internal Memory - Character Generator ROM (CGROM) : 9,600 bits (240 characters x 5 x 8 dot) - Character Generator RAM (CGRAM) : 64 x 8 bits (8 characters x 5 x 8 dot) - Segment Icon RAM (SEGRAM) : 16 x 8 bits (96 icons max.) - Display Data RAM (DDRAM) : 96 x 8 bits (96 characters max.) * Low power operation - Power supply voltage range : 2.7 ~ 5.5 V (VDD) - LCD Drive voltage range : 3.0 ~ 13.0 V (VDD - V5) * CMOS process * Programmable duty cycle : 1/17, 1/33 (refer to Table 1.) * Internal oscillator with an external resistor * Bare chip available
KS0078
Table 1. Programmable duty cycles 5-dot font width Display Line Numbers 1 2 4 6-dot font width Display Line Numbers 1 2 4 1/17 1/33 1/33 Duty Ratio 1/17 1/33 1/33 Duty Ratio
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Single-chip Operation Displayable characters 1 line of 48 characters 2 lines of 48 characters 4 lines of 24 characters Possible icons 80 80 80
Single-chip Operation Displayable characters 1 line of 40 characters 2 lines of 40 characters 4 lines of 20 characters Possible icons 96 96 96
KS0078 BLOCK DIAGRAM
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
IE
OSC1
OSC2
Oscillator Power On Reset (POR)
Timing Generator
RESET IM 8 / RS/ CS E/ SCLK RW/ SID
System Interface Serial 4 bit 8 bit Instruction Register (IR) Display Data RAM (DDRAM) Address Counter 96 x 8 bits 34 bit Shift Register Common Driver
/7
Instruction Decoder
COM0 COM33
7 7 /
Data Register (DR)
/ /8
DB4 DB7
Input/ Output Buffer
8 /
8 / /8
120 bit Shift Register 120 bit Latch Circuit Segment Driver
DB3 DB1
SEG1 SEG120
Busy Flag
/3
/7
/8
/8
DB0/ SOD
Ch aracter Gen erator RAM(CGRAM) 64 b ytes Ch aracter Gen erator ROM(CGROM) 960 0 b its
SegmentRAM (SEGRAM) 16 bytes
Cursor and Blink Controller
Vci
LCD Driver Voltage Selector
C1
Voltage Converter
/5 / 5/6
C2 V5OUT2 V5OUT3
Parallel / Serial Converter and Smooth Scroll Circuit
V1 - V5
VDD
GND (VSS)
KS0078 PAD CONFIGURATION
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148
SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43
Y
(0, 0)
X
chip size : 5340 x 8740 PAD size :100 x 100 unit : m
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
VDD OSC2 OSC1 RESET IM IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1
KS0078 PAD LOCATION
PAD NO. PAD NAME COORDINATE XYPAD NO. PAD NAME
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
COORDINATE X-
PAD NO.
PAD NAME
COORDINATE XY-
PAD NO.
PAD NAME
COORDINATE XY-
Y665 540 415 290 165 40 -8 4 - 2 09 - 3 34 - 4 59 - 5 84 - 7 09 - 8 34 - 9 59 -1 084 -1 209 -1 334 -1 459 -1 584 -1 822 -1 947 -2 072 -2 197
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S E G7 9 SEG 8 0 SEG 8 1 SEG 8 2 SEG 8 3 SEG 8 4 SEG 8 5 SEG 8 6 SEG 8 7 SEG 8 8 SEG 8 9 SEG 9 0 SEG 9 1 SEG 9 2 SEG 9 3 SEG 9 4 SEG 9 5 SEG 9 6 SEG 9 7 SEG 9 8 SEG 9 9 SEG 1 0 SEG 1 0
-2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04 -2 5 04
3540 341 329 316 304 291 279 266 254 241 229 216 204 191 179 166 154
1415
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
S E G 1 02 S E G 1 03 S E G 1 04 S E G 1 05 S E G 1 06 S E G 1 07 S E G 1 08 S E G 1 09 S E G 1 10 S E G 1 11 S E G 1 12 S E G 1 13 S E G 1 14 S E G 1 15 S E G 1 16 S E G 1 17 S E G 1 18 S E G 1 19 S E G 1 20 C OM 9 C O M 10 C O M 11 C O M 12
-2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
C O M 13 C O M 14 C O M 15 C O M 16 C O M 25 C O M 26 C O M 27 C O M 28 C O M 29 C O M 30 C O M 31 C O M 32 C O M 33 VD D OSC 2 OSC 1 R ES E T IM IE VSS 1 R S/C S R W /S I D E /S C L K
-2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 -2 5 0 4 - 1 750 - 1 625 - 1 500 - 1 375 - 1 250 - 1 125 - 1 000 -8 75 -7 50 -6 25
- 2 322 - 2 447 - 2 572 - 2 697 - 2 822 - 2 947 - 3 072 - 3 197 - 3 322 - 3 447 - 3 572 - 3 697 - 3 822 - 4 119 - 4 119 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
D B0 / SO D D B1 D B2 D B3 D B4 D B5 D B6 D B7 Vci C2 C1 VSS 2 V5 OU T 2 V5 OU T 3 V5 V4 V3 V2 V1 C O M 24 C O M 23 C O M 22 C O M 21
- 5 00 - 3 75 - 2 50 - 1 25 0 125 250 375 500 625 750 875 1 0 00 1 1 25 1 2 50 1 3 75 1 5 00 1 6 25 1 7 50 2504 2504 2504 2504
-4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 -4 1 1 9 - 3 822 - 3 697 - 3 572 - 3 447
142 129 116 104 915 790
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD COO RDINATE CONTINUED
COORDINATE XYCOORDINATE XYCOORDINATE XYCOORDINATE XY-
PAD NO.
PAD NAME
PAD NO.
PAD NAME
PAD NO.
PAD NAME
PAD NO.
PAD NAME
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
C O M 20 C O M 19 C O M 18 C O M 17 COM 8 COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 SEG 9 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 1 0
2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04 2 5 04
-3 3 2 2 -3 197 -3 072 -2 947 -2 822 -2 697 -2 572 -2 447 -2 322 -2 197 -2 072 -1 947 -1 822 -1 584 -1 459 -1 334 -1 209 -1 084 - 9 59 - 8 34 - 7 09 - 5 84 - 4 59
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
SEG 1 1 SEG 1 2 SEG 1 3 SEG 1 4 SEG 1 5 SEG 1 6 SEG 1 7 SEG 1 8 SEG 1 9 SEG 2 0 SEG 2 1 SEG 2 2 SEG 2 3 SEG 2 4 SEG 2 5 SEG 2 6 SEG 2 7 SEG 2 8 SEG 2 9 SEG 3 0 SEG 3 1 SEG 3 2 SEG 3 3
2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504
-334 - 2 09 -8 4 40 165 290 415 540 665 790 915 1 0 40 1 1 65 1 2 90 1 4 15 1 5 40 1 6 65 1 7 90 1 9 15 2 0 40 2 1 65 2 2 90 2 4 15
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161
SEG 3 4 SEG 3 5 SEG 3 6 SEG 3 7 SEG 3 8 SEG 3 9 SEG 4 0 SEG 4 1 SEG 4 2 SEG 4 3 SEG 4 4 SEG 4 5 SEG 4 6 SEG 4 7 SEG 4 8 SEG 4 9 SEG 5 0 SEG 5 1 SEG 5 2 SEG 5 3 SEG 5 4 SEG 5 5 SEG 5 6
2504 2504 2504 2504 2504 2504 2504 2504 2504 2 1 87 2 0 62 1 9 37 1 8 12 1 6 87 1 5 62 1 4 37 1 3 12 1 1 87 1 0 62 937 812 687 562
2540 2 6 65 2 7 90 2 9 15 3 0 40 3 1 65 3 2 90 3 4 15 3 5 40 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183
SEG 5 7 SEG 5 8 SEG 5 9 SEG 6 0 SEG 6 1 SEG 6 2 SEG 6 3 SEG 6 4 SEG 6 5 SEG 6 6 SEG 6 7 SEG 6 8 SEG 6 9 SEG 7 0 SEG 7 1 SEG 7 2 SEG 7 3 SEG 7 4 SEG 7 5 SEG 7 6 SEG 7 7 SEG 7 8
437 312 187 62 -6 2 - 1 87 - 3 12 - 4 37 - 5 62 - 6 87 - 8 12 - 9 37 - 1 062 - 1 187 - 1 312 - 1 437 - 1 562 - 1 687 - 1 812 - 1 937 - 2 062 - 2 187
4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19 4 1 19
KS0078 PAD DESCRIPTION
PAD (NO) INPUT/ OUTPUT VDD (60) VSS1,VSS2 (66,81) V1-V5 (88-84) Vci (78) SEG1-SEG120 (106-183, 1-42) COM0-COM33 (105-89, 43-59) OSC1,OSC2 (61,62) -
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
NAME
DESCRIPTION
INTERFACE
for logical circuit(+3V,+5V) 0V(GND) Power supply Input Output Bias voltage level for LCD driving. Power supply
Input voltage to the voltage converter to generate LCD drive voltage(Vci = 1.0 -4.5V). Segment output Segment signal output for LCD drive.
LCD
Output
Common output Common signal output for LCD drive.
LCD
C1,C2 (80,79)
Input (OSC1), Output (OSC2) Input
Oscillator
When use internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1.
External resistor/oscillator (OSC1) External capacitance -
RESET (63) IE (65)
Input Input
V5OUT2(82)
Output
V5OUT3(83)
External To use the voltage converter(2 times /3 times), capacitance input these pins must be connected to the external capacitance. Reset pin Initialized to Low Select pin When IE = "High", Instruction set is of selected as Table 6. instruction When IE = "Low", Instruction set is selected as set Table 10. Two times The value of Vci is converted two times. To converter use three times converter, the same output capacitance as that of C1-C2 should be connected here. Three times The value of Vci is converted three times. converter output
V5 capacitance
V5
KS0078 PAD DESCRIPTION (continued)
PAD (NO) IM (64) INPUT/ OUTPUT Input
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
NAME Interface mode selection Register select/ Chip select
DESCRIPTION Select Interface mode with the MPU. In IM = "Low" : Serial mode, In IM = "High" : 4-bit/8-bit bus mode. In bus mode, used as register selection input. In RS/CS = "High", Data register is selected. In RS/CS = "Low", Instruction register is selected. In serial mode, used as chip selection input. In RS/CS = "Low", selected. When RS/CS = "High", not selected.(Low access enable)
INTERFACE -
RS/CS (67)
Input
MPU
RW/SID (68)
Input
In bus mode, used as read/write selection input. Read_write/ In RW/SID = "High", read operation. When Serial input data RW/SID = "Low", write operation. In serial mode, used for data input pin. Read_write enable/Serial clock Data bus 0 bit/Serial output data Data bus 1- 7 In bus mode, used as read_write enable signal. In serial mode, used as serial clock input pin. In 8-bit bus mode, used as lowest bi-directional data bit. During 4-bit bus mode, Open this pin. In serial mode, used as serial data output pin. If not in read operation, open this pin. In 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode or serial mode, open these pins. In 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for Busy Flag output. During serial mode, open these pins.
MPU
E/SCLK (69)
Input
MPU
DB0/SOD (70)
Input_Output/ Output
MPU
DB1-DB3 (71-73)
Input. Output
MPU
DB4-DB7 (74-77)
MPU
KS0078 FUNCTION DESCRIPTION
System Interface
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
This chip has all three kinds interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit) is selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low").
Table 2. Various kinds of operations according to RS and R/W bits. RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy flag(DB7) and address counter (DB0 ~ DB6) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR)
Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High(Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.
KS0078
Display Data RAM (DDRAM)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
DDRAM stores display data of maximum 96 x 8 bits (96 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Fig-1.)

Fig-1. DDRAM Address 1) Display of 5-dot font width character 5-dot 1 line display In the case of 1 line display with 5-dot font, the address range of DDRAM is 00H ~ 5FH. (Refer to Fig-2)

!

"!
Fig-2. 1-line X 48ch. display

KS0078
5-dot 2 line display
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
In the case of 2 line display with 5-dot font, the address range of DDRAM is 00H ~ 2FH, 40H ~ 6FH. (refer to Fig-3)

!

"!
Fig-3. 2-line X 48ch. display (5-dot font width)
KS0078
5-dot 4 line display
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
In the case of 4 line display with 5-dot font, the address range of DDRAM is 00H ~ 17H, 20H ~ 37H, 40H ~ 57H, 60H ~ 77H. (refer to Fig-4)

Fig-4. 4-line X 24ch. display (5-dot font width)
KS0078
2) Display of 6-dot font width character 6-dot 1 line display
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
In the case of 1 line display with 6-dot font, the address range of DDRAM is 00H ~ 5FH. (refer to Fig-5)

!

"!
Fig-5. 1-line X 40ch. display
KS0078
6-dot 2 line display
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
In the case of 2 line display with 6-dot font, the address range of DDRAM is 00H ~ 2FH, 40H ~ 6FH. (refer to Fig-6)

!

"!
Fig-6. 2-line X 40ch. display (6-dot font width)
KS0078
6-dot 4 line display
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
In the case of 4 line display with 6-dot font, the address range of DDARM is 00H ~ 17H, 20H ~ 37H, 40H ~ 57H, 60H ~ 77H. (refer to Fig-7)

!! "

Fig-7. 4-line X 20ch. display (6-dot font width)
KS0078
Timing Generation Circuit
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Timing generation circuit generates clock signals for the internal operations. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0~DB6 Cursor/Blink Control Circuit It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD Driver Circuit LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from SEGRAM/CGRAM/CGROM is transferred to 120-bit segment latch serially, which is stored to 120-bit shift latch. When each common is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. In 1-line display mode, COM0 ~ COM17 have 1/17 duty, and in 2-line or 4-line mode, COM0 ~ COM33 have 1/33 duty ratio.
KS0078
CGROM (Character Generator ROM)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM has 5 x 8-dot 240 character pattern. (refer to Table 3) Table 3. CGROM Character Code Table
KS0078
CGRAM (Character Generator RAM)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGRAM has up to 5 x 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used. (Refer to Table 4)
Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM) 1) 5 x 8 dot Character pattern
!" !
!#
!# $ $( $ $ $ $ $ $ * * ) , * * )
( , ) ) , ,
$ %&'
,

KS0078
2) 6 x 8 dot Character pattern
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
#$ # ! * *
#% + + & + & +
#% & & & & & &
& '()

*
1. When BE(Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In displaying 5-dot font width, when B1 = "1", enabled dots of P0 ~ P4 will blink, and When B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen. In displaying 6-dot font width, when B1 = "1", enabled dots of P0 ~ P5 will blink, and When B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen. 2. "X" : Don't care
KS0078
SEGRAM (Segment Icon RAM)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17) makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data. (refer to Table 5 and Fig-8) Table 5. Relationship between SEGRAM address and display pattern

*

# " # ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! "

" # " # " # " # " # " # " # "
" # " # " # " # " # " # " # " " " " " " " " "" "# # # # # # # #
1. B1, B0 : Blinking control bit Control Bit BE B1 B0 0 X X 10 0 10 1 11 X Blinking Port 5-dot font width No blink No blink D4 D4 ~ D0 6-dot font width No blink No blink D5 D5 ~ D0
2. S1~S80 : Icon pattern ON/OFF in 5-dot font width S1~S96 : Icon pattern ON/OFF in 6-dot font width 3. "X" : Don't care

KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
1) 5-dot font width (FW = 0)

S E G 1 S E G 2 S E G 3 S E G 4 S E G 5
S E G 7 6 S E G 7 7 S E G 7 8 S E G 7 9 S E G 8 0
S E G 1 1 1
S E G 1 1 2
S E G 1 1 3
S E G 1 1 4
S E G 1 1 5
S E G 1 1 6
S E G 1 1 7
S E G 1 1 8
S E G 1 1 9
S E G 1 2 0
2) 6-dot font width (FW = 1)

S E G 1 S E G 2 S E G 3 S E G 4 S E G 5
S E G 9 1
S E G 6
SSSSS EEEEE GGGGG 99999 23456
S E G 1 0 9
S E G 1 1 0
S E G 1 1 1
S E G 1 1 2
S E G 1 1 3
SSSS EEEE GGGG 1111 1111 4567
SSS EEE GGG 111 112 890
Fig-8. Relationship between SEGRAM and segment display
KS0078 INSTRUCTION DESCRIPTION
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
OUTLINE To overcome the speed difference between internal clock of KS0078 and MPU clock, KS0078 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 6/10) Instruction can be divided largely four kinds, (1) KS0078 function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal RAM (3) data transfer instructions with internal RAM (4) others . The address of internal RAM is automatically increased or decreased by 1. When IE = "High", KS0078 is operated according to Instruction Set 1(Table 6) and when IE = "Low", KS0078 is operated according to Instruction Set 2(Table 10).
* Note : During internal operation, Busy Flag (DB7) is read High. Busy Flag check must precede the next instruction. When you make a MPU program with checking the Busy Flag(DB7), it must be necessary 1/2Fosc for executing the next instruction by falling E signal after the Busy Flag(DB7) goes to "Low".
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(1) INSTRUCTION DESCRIPTION 1 (IE = "High")
Table 6. Instruction Set 1 Instruction RE Instruction Code R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Clear Display Return Home X 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Set power down mode bit. PD = "1" :power down mode set, PD = "0" :power down mode disable Assign cursor moving direction. I/D = "1" : increment, I/D = "0" : decrement and display shift enable bit. S = "1" : make display shift of the enabled lines by the DS4 -DS1 bits in the Shift Enable instruction. S = "0":display shift disable Segment bi-direction function. 1 0 0 0 0 0 0 0 1 1 BID BID = "1" : Seg120 Seg1, BID = "0" : Seg1 Seg120. Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode. Description Execution Time (fosc = 270 kHz) 1.53ms
0
0
0
0
0
0
0
0
0
1
X
1.53ms
Power Down Mode
1
0
0
0
0
0
0
0
0
1
PD
39s
Entry Mode Set
0
0
0
0
0
0
0
0
1
I/D
S
39s
Display ON/OFF Control
0
0
0
0
0
0
0
1
D
C
B
39s
Extended function set
1
0
0
0
0
0
0
1
FW
B/W
NW
39s
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(Table 6. continued)
Instruction RE
Instruction Code R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S
Description
Execution Time (fosc = 270 kHz)
Cursor or Display Shift
0
0
0
0
0
0
1
S/C R/L
X
X
Shift Enable
1
0
0
0
0
0
1
DS4 DS3 DS2 DS1
Scroll Enable
1
0
0
0
0
0
1
HS4 HS3 HS2 HS1
0 Function Set
0
0
0
0
1 DL
N
RE(0) DH REV
1
0
0
0
0
1
DL N
RE(1) BE
0
Cursor or display shift. S/C = "1" : display shift, S/C = "0" : cursor shift, R/L = "1" : shift to right, R/L = "0" : shift to left. (when DH = "1") Determine the line for display shift . DS1 = "1/0": 1st line display shift enable/disable DS2 = "1/0": 2nd line display shift enable/disable DS3 = "1/0": 3rd line display shift enable/disable DS4 = "1/0": 4th line display shift enable/disable. (when DH = "0") Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable. Set interface data length (DL = "1" : 8-bit, DL = "0" : 4-bit), numbers of display line when NW = "0", (N = "1" : 2-line, N = "0" : 1-line), extension register, RE("0"), shift/scroll enable DH = "1" : display shift enable DH = "0" : dot scroll enable. reverse bit REV = "1" : reverse display, REV = "0" : normal display. Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable
39s
39s
39s
39s
39s
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(Table 6. continued)
Instruction RE
Instruction Code R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S
Description
Execution Time (fosc = 270 kHz) 39s
Set CGRAM Address Set SEGRAM Address Set DDRAM Address Set Scroll Quantity Read Busy flag and Address Write Data Read Data
0
0
0
0
1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
1
0
0
0
1
X
X AC3 AC2 AC1 AC0
Set SEGRAM address in address counter.
39s
0
0
0
1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address counter.
39s
1
0
0
1
X SQ5 SQ4 SQ3 SQ2 SQ1 SQ0
Set the quantity of horizontal dot scroll. Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = "1" : busy state, BF = "0" : ready state. Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
39s
X
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
0s
X X
1 1
0 1
D7 D6 D7 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
43s 43s
* Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the "E" signal after the Busy Flag (DB7) goes to "Low". 2. "X" Don't care
KS0078
1) Display Clear
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1").
2) Return Home : (RE = 0)

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. site and return display to its original status, if shifted. Contents of DDRAM does not change.
Return cursor to its original
3) Power Down Mode Set : (RE = 1)

Power down mode enable bit set instruction. When PD = "High", it makes KS0078 suppress current consumption except the current needed for data storage by executing next three functions. 1. make the output value of all the COM/SEG ports VDD 2. make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to "Low" 3. disable voltage converter to remove the current through the divide resistor of power supply. This instruction can be used as power sleep mode. When PD = "Low", power down mode becomes disabled.
KS0078
4) Entry Mode Set (RE = 0)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
./
+
+
+
+
+
+
+
+

Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the Shift Enable instruction is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not performed.
(RE = 1)

-.
*
*(
*
*
*
*
*
*

Set the data shift direction of segment in the application set. BID : Data Shift Direction of Segment When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG120. When BID = "High", segment data shift direction is set to reverse from SEG120 to SEG1. By using this instruction, the efficiency of application board area can be raised. * The BID setting instruction is recommended to be set at the same time level of function set instruction. * DB1 bit must be set to "1".
KS0078
5) Display ON/OFF Control ( RE = 0 )

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

#
+
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off.
6) Extended Function Set ( RE = 1 )

FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of CGRAM.(refer to Fig-9) When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270 kHz, inversion has 370 ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-bit
s p a c e CGROM character ont (5-dot )
6-bit
CGRAM character f ont (6-dot )
8 b i t
8 b i t
-
-
(CGROM)
(CGRAM)
Fig-9. 6-dot font width CGROM/CGRAM
7) Cursor or Display Shift (RE = 0)

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data.(Refer to Table 7) During 2-line mode display, cursor moves to the 2nd line after 48th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 24th digit of the current line. Note that display shift is performed simultaneously in all the line enabled by DS1 DS4 in the Shift Enable instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. During low power consumption mode, display shift may not be performed normally.
Table 7. Shift patterns according to S/C and R/L bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
KS0078
8) Shift/Scroll Enable (RE = 1) (DH = 0)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

HS : Horizontal Scroll per Line Enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)
(DH = 1)

DS : Display Shift per Line Enable This instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each line. If DS1 and DS2 is set to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4) are set to "Low" (disable), no display is shifted.
Table 8. Relationship between DS and COM signal Enable bit Enabled common signals during shift HS1/DS1 HS2/DS2 HS3/DS3 HS4/DS4 COM1 ~ COM8 COM9 ~ COM16 COM17 ~ COM24 COM25 ~ COM32 The part of display line that corresponds to enabled common signal can be shifted. Description

KS0078
9) Function Set (RE = 0)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low". DH : Display shift enable selection bit. When DH = "High", enable display shift per line. When DH = "Low", enable smooth dot scroll. This bit can be accessed only when IE pin input is "High". REV : Reverse enable bit When REV = "High", all the display data are reversed. i.e. all the black and black dots become white. When REV = "Low", the display mode set normal display.
white dots become
KS0078
(RE = 1)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of shift/scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM.
10) Set CGRAM Address (RE = 0)

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
11) Set SEGRAM Address (RE = 1)

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
KS0078
12) Set DDRAM Address (RE = 0)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "5FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H" to "6FH". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "37H" in the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line.
13) Set Scroll Quantity (RE = 1)

Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 9). In this case of KS0078 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.
Table 9. Scroll quantity according to HDS bits SQ5 0 0 0 0 : 1 1 SQ4 0 0 0 0 : 0 1 SQ3 0 0 0 0 : 1 X SQ2 0 0 0 0 : 1 X SQ1 0 0 1 1 : 1 X SQ0 0 1 0 1 : 1 X Function No shift shift left by 1-dot shift left by 2-dot shift left by 3-dot : shift left by 47-dot shift left by 48-dot
KS0078
14) Read Busy Flag & Address

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

#$
%
%
%
%
%
%
%
This instruction shows whether KS0078 is in internal operation or not. If the resultant BF is High, the internal operation is in progress and you have to wait until BF to be Low, which by then the next instruction can be performed. In this instruction you can read the value of address counter.
15) Write data to RAM

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
16) Read data from RAM

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, the correct RAM data can be obtained from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 as in read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by read instruction.
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(2) INSTRUCTION DESCRIPTION 2 (IE = "LOW")
Table 10. Instruction Set 2 Execution Time (fosc = 270 kHz) Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction. I/D = "1" : increment, I/D = "0" : decrement. and display shift enable bit. S = "1" :make entire display shift of all lines during DDRAM write, S = "0":display shift disable Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode Cursor or display shift. S/C = "1" : display shift, S/C = "0" : cursor shift, R/L = "1" : shift to right, R/L = "0" : shift to left 1.53ms
Instruction RE
Instruction Code R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S
Description
Clear Display Return Home
X
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
0
1
X
1.53ms
Entry Mode Set
X
0
0
0
0
0
0
0
1
I/D
S
39s
Display ON/OFF Control
0
0
0
0
0
0
0
1
D
C
B
39s
Extended function set
1
0
0
0
0
0
0
1
FW B/W NW
39s
Cursor or Display Shift
0
0
0
0
0
0
1
S/C R/L
X
X
39s
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(Table 10. continued) Execution Time (fosc = 270 kHz) Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable Set interface data length DL = "1" : 8-bit, DL = "0" : 4-bit numbers of display line when NW = "0", N = "1" : 2-line, N = "0" : 1-line extension register, RE("0"), Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable Set CGRAM address in address counter.
Instruction RE
Instruction Code R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S
Description
Scroll Enable
1
0
0
0
0
0
1 HS4 HS3 HS2 HS1
39s
0 Function Set 1
0
0
0
0
1 DL
N
RE(0)
X
X
39s
0
0
0
0
1
DL N
RE(1) BE
0
39s
Set CGRAM Address Set SEGRAM Address Set DDRAM Address Set Scroll Quantity Read Busy flag and Address Write Data Read Data
0
0
0
0
1 AC5 AC4 AC3 AC2 AC1 AC0
39s
1
0
0
0
1
X
X AC3 AC2 AC1 AC0 Set SEGRAM address in address counter.
39s
0
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address counter.
39s
1
0
0
1
X
QC5 QC4 QC3 QC2 QC1 QC0
Set the quantity of horizontal dot scroll. Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = "1" : busy state, BF = "0" : ready state. Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
39s
X
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
0s
X X
1 1
0 1
D7 D6 D7 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
43s 43s
* Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the "E" signal after the Busy Flag (DB7) goes to "Low". 2. "X" Don't care
KS0078
1) Display Clear

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. And entry mode is set to increment mode (I/D = "1").
2) Return Home

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. site and return display to its original status, if shifted. Contents of DDRAM does not change.
Return cursor to its original
3) Entry Mode Set

Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates identically to the DDRAM, when reading from or writing to CGRAM/SEGRAM. When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not moving. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of entire display is not performed.
KS0078
4) Display ON/OFF Control ( RE = 0 )

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off.
5) Extended Function Set ( RE = 1 )

FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of CGRAM.(Refer to Fig-10) When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270 kHz, inversion has 370 ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
KS0078
6-bit
s p a c e CGROM character f ont (5-dot )
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-bit
CGRAM character f ont (6-dot )
8 b i t
8 b i t
-
(CGROM)
(CGRAM)
Fig-10. 6-dot font width CGROM/CGRAM
6) Cursor or Display Shift (RE = 0)

Shift right/left cursor position or display, without writing or reading of display data. This instruction is used to correct or search display data.(Refer to Table 7) During 2-line mode display, cursor moves to the 2nd line after 48th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 24th digit of the current line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed.
Table 11. Shift patterns according to S/C and R/L bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
KS0078
7) Scroll Enable (RE = 1)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

HS : Horizontal Scroll per Line Enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)
8) Function Set c (RE = 0)

DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, t means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low".

KS0078
d (RE = 1)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM.
9) Set CGRAM Address (RE = 0)

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 10) Set SEGRAM Address (RE = 1)

Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU.
KS0078
11) Set DDRAM Address (RE = 0)

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "5FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H" to "6FH". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "17H" in the 1st line, from "20H" to "37H" in the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line.
12) Set Scroll Quantity (RE = 1)

Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 12). In this case of KS0078 execute dot smooth scroll from 1 to 48 dots.
Table 12. Scroll quantity according to HDS bits SQ5 0 0 0 0 : 1 1 SQ4 0 0 0 0 : 0 1 SQ3 0 0 0 0 : 1 X SQ2 0 0 0 0 : 1 X SQ1 0 0 1 1 : 1 X SQ0 0 1 0 1 : 1 X Function No shift shift left by 1-dot shift left by 2-dot shift left by 3-dot : shift left by 47-dot shift left by 48-dot
KS0078
13) Read Busy Flag & Address

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

This instruction shows whether KS0078 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and should wait until BF to become "Low". which by then the next instruction can be performed. In this instruction value of address counter can also be read.
14) Write data to RAM

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
15) Read data from RAM

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If the RAM data is read severa l times without RAM address set instruction before read operation, the correct RAM data from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 like read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by read instruction.
KS0078 INTERFACE WITH MPU
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
KS0078 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. Hence, both types of 4 or 8-bit MPU can be used. In case of 4-bit bus mode, data transfer is performed by twice to transfer 1 byte data. (1) When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by twice. Busy Flag outputs "High" after the second transfer is ended. (2) When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7. (3) If IM is set to "Low", serial transfer mode is set.
KS0078
Interface with MPU in Bus Mode
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
1) Interface with 8-bits MPU If 8-bits MPU is used, KS0078 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7 need to interface each other. Example of timing sequence is shown below.

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Fig 11. Example of 8-bit Bus Mode Timing Sequence 2) Interface with 4-bits MPU If 4-bits MPU is used, KS0078 can connect directly with this. In this case, port E, RS, R/W and DB4 to DB7 need to interface each other. The transfer is performed by twice. Example of timing sequence is shown below.
RS
R/W
E Internal signal
Internal operation No Busy
DB7
D7
D3
Busy
AC3
AC3
D7
D3
INSTRUCTION
Busy Flag Check
Busy Flag Check
INSTRUCTION
Fig 12. Example of 4-bit Bus Mode Timing Sequence
KS0078
Interface with MPU in Serial Mode
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing transfer clock), SID (serial input data), and SOD (serial output data), are used. If KS0078 is to be used with other chips, chip select port (CS) can be used. By setting CS to "Low", KS0078 can receive SCLK input. If CS is set to "High", KS0078 reset the internal transfer counter. Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write control bit (R/W), register selection bit (RS), and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are detected by KS0078, it makes serial transfer counter reset and ready to receive next information. The next input data are register selection bit that determine which register will be used, and read write control bit that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (Refer to Fig 13. Fig 14) (1) Write Operation (R/W = 0) After start byte is transferred from MPU to KS0078, 8-bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. To transfer several bytes continuously without changing RS bit and R/W bit, start byte transfer is needed only at first starting time. i.e., after first start byte is transferred, real data succeeding can be transferred. (2) Read Operation (R/W = 1) After start byte is transferred to KS0078, MPU can receive 8-bit data through the SOD port at a time from the LSB. Wait time is needed to insert between start byte and data reading, as internal reading from RAM requires some delay. Continuous data reading is possible such as serial write operation. It also needs only one start bytes, only if you insert some delay between reading operations of each byte. During the reading operation, KS0078 observes succeeding 5 "High" from MPU. If it is detected, KS0078 restarts serial operation at once and ready to receive RS bit. So in continuous reading operation, SID port must be "Low".
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
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KS0078

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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
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Fig 14. Timing Diagram of Continuous Data Transfer
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
APPLICATION INFORMATION ACCORDING TO LCD PANEL
1) LCD Panel : 48 character x 1 line format (5-dot font,1/17 duty)

2) LCD Panel : 48 character x 2 line format (5-dot font, 1/33 duty)

KS0078
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
3) LCD Panel : 24 character x 4 line format (5-dot font, 1/33 bias)

KS0078

KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
4) LCD Panel : 20 character x 4 line format (6-dot font, 1/33 bias)

KS0078
KS0078 INITIALIZING
1) Initializing by Internal Reset Circuit
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
When the power is turned on, KS0078 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. c Display Clear instruction Write "20H" to all DDRAM d Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode RE = 0 : Extension register disable BE = 0 : CGRAM/SEGRAM blink OFF DH = 0 : Horizontal scroll enable REV = 0 : Normal display (Not reversed display) e Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF f Set Entry Mode instruction I/D = 1 : Increment by 1 S = 0 : No entire display shift BID = 0 : Normal direction segment port g Set Extension Function instruction FW = 0 : 5-dot font width character display B/W = 0 : Normal cursor (8th line) NW = 0 : Not 4-line display mode, 2-line mode is set because of N("1") h Enable Shift instruction HS = 0000 : Scroll per line disable DS = 0000 : Shift per line disable i Set scroll Quantity instruction SQ = 000000 : Not scroll 2) Initializing by Hardware RESET input When RESET pin = "Low", KS0078 can be initialized like the case of power on reset. During the power on reset operation, this pin is ignored.
KS0078 INITIALIZING BY INSTRUCTION
1) 8-bit interface mode
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Power on
Wait for more than 20 ms after VDD rises to 4.5V (DL="1") Function set DL RS 0 RW DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 DL (1) N 0 x x N
Condition: 270 kHz
0 1 0 1
4-bit interface 8-bit interface 1-line mode 2-line mode
Wait for more than 39 s 0 D Dsplay ON/OFF Control RS 0 RW DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 D C B B Wait for more than 39 s Clear Dsplay RS 0 RW 0 DB7 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 C 1 0 1 0 1 display off display on cursor off cursor on blink off blink on
Wait for more than 0 1 0 S 1
Entry Mode Set RS 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S
I/D
decrement mode increment mode entire shift off entire shift on
Initialization end
KS0078
2) 4-bit interface mode
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Power on
Wait for more than 20 ms after VDD rises to 4.5V (DL="0") Function set DL RS 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL (0) x x x x N
Condition: 270 kHz
0 1 0 1
4-bit interface 8-bit interface 1-line mode 2-line mode
Wait for more than 39s
Function set RS 0 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 N 0 x 1 x 0 x x x x x x x x x
Wait for more than 39s 0 Dsplay ON/OFF Control RS 0 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 D 0 C 0 B x x x x x x x x B D C 1 0 1 0 1 display off display on cursor off cursor on blink off blink on
Wait for more than 39s
Clear Dsplay RS 0 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 x x x x x x x x
Wait for more than 1.53ms
Entry ModeSet RS 0 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 I/D 0 S x x x x x x x x
0 I/D 1 0 1
decrement mode increment mode entire shift off entire shift on
S
Initialization end
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE
1) IE = "Low"

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2) IE = "High"
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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

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KS0078 FRAME FREQUENCY
1) 1/17 duty cycle

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
VDD

000

000
#1

Item 5-dot font width 1-line selection period Frame frequency 240 clocks 66.2Hz
Display Font Width 6-dot font width 288 clocks 55.1Hz * fosc = 270 kHz (1 clock = 3.7)
2) 1/33 duty cycle

VDD

333

333
&4

Item 5-dot font width 1-line selection period Frame frequency 120 clocks 68.2Hz
Display Font Width 6-dot font width 144 clocks 56.8Hz * fosc = 270 kHz (1 clock = 3.7)
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
1) When an external power supply is used

2) When an internal booster is used
(Boosting twice) VDD + 1F + VCI GND C1 C2 V5OUT2 V5OUT3 VDD V1 V2 V3 V4 V5 R R R0 R R 1F + 1F + VDD + 1F +
(Boosting three times)
VCI GND C1 C2 V5OUT2 V5OUT3
VDD V1 V2 V3 V4 V5 R R R0 R R
1F +
Can be detached If not using powr down mode
Can be detached If not using powr down mode
*
1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three times. 2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice. 3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to Table 13)
Table 13. Duty Ratio and Power Supply for LCD Driving Item Number of lines Duty ration BIas Divided resistance R R0 1 1/17 1/5 R R Data 2 or 4 1/33 1/6.7 R 2.7R
KS0078 MAXIMUM ABSOLUTE RATE
Characteristic Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage Operating Temperature Storage Temperature
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Symbol VDD VLCD VIN TOPR TSTG
Value -0.3 to +7.0 VDD -15.0 to VDD +0.3 -0.3 to VDD +0.3 -30 to +85 -55 to +125
Unit V V V C C
* Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5)
KS0078 ELECTRICAL CHARACTERISTICS
DC Characteristics
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(VDD = 2.7V to 5.5V, Ta=-30 to +85C) Characteristic Operating Voltage Supply Current Symbol VDD IDD Condition Internal oscillation or external clock. (VDD=3.0V,fosc=270KHz) Input Voltage (1) (Except OSC1) VIH1 VIL1 VDD=2.7 to 3.0 VDD=3.0 to 5.5 Input Voltage (2) (OSC1) Output Voltage (1) (DB0 to DB7) Output Voltage(2) (except DB0 to DB7) Voltage Drop VIH2 VIL2 VOH1 VOL1 VOH2 VOL1 VdCOM VdSEG Input Leakage Current Low Input Current IIL IIN VIN=0V to VDD VIN=0V, VDD=3V (PULL UP) Internal Clock (external Rf) External Clock fEC duty tR, tF Voltage Converter Out2 (Vci = 4.5V) Voltage Converter Out3 (Vci = 2.7V) Voltage Converter Input LCD Driving Voltage Vci VLCD VDD-V5 1/5 Bias 1/6.7 Bias 1.0 3.0 3.0 4.5 13.0 13.0 V VOUT3 VOUT2 Ta = 25 C, C=1 F, IOUT = 0.25mA, fOSC=270KHz -4.3 -5.1 fOSC Rf=91k 2% (VDD=5V) 125 45 -3.0 270 50 -4.2 410 55 0.2 KHz % s V 190 270 350 KHz IOH=-0.1mA IOL=0.1 mA IO=-40 A IO=40 A IO= 0.1mA 0.7VDD -0.3 -0.3 0.7VDD 0.75VDD 0.8VDD -1 -10 -50 VDD 0.2VDD 0.6 VDD 0.2VDD 0.2VDD 0.2VDD 1 1 1 -120 A V V V V Min 2.7 Typ 0.15 Max 5.5 0.3 Unit V mA
KS0078 AC Characteristics
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(VDD = 4.5 to 5.5V, Ta=-30 to +85 C) Mode Item E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) (1) Write Mode (refer to Fig-15) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) (2) Read Mode (refer to Fig-16) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) (3) Serial Interface Mode (refer to Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tc, tR, tF tw tsu1 tH1 tsu2 tH2 tc tR,tF tw tsu tH tD tDH tc tR,tF tw tsu1 tH1 tsu2 t H2 tD tDH Min 500 230 40 10 60 10 500 230 40 10 5 0.5 200 60 20 100 100 5 Typ Max 20 20 160 20 50 160 ns s ns ns Unit
KS0078 AC Characteristics (continued)
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(VDD=2.7 to 4.5V, Ta=-30 to +85 C) Mode Item E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) (4) Write Mode (refer to Fig-15) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) (5) Read Mode (refer to Fig-16) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) (6) Serial Interface Mode (refer to Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tc, tR, tF tw tsu1 th1 tsu2 tH2 tc tR,tF tw tsu tH tD tDH tc tR,tF tw tsu1 tH1 tsu2 t H2 tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 1 400 60 20 200 200 5 Typ Max 25 25 360 20 50 360 ns s ns ns Unit
KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
VIH1
RS
VIL1 tsu1 tH1
R/W
VIL1 tw VIH1 VIL1 tR VIH1 tSU2 VIH1 VIL1 tH2 tH1 tF
VIL1
E
VIL1
DB0~DB7
VIL1
Valid Data tc
VIH1 VIL1
Fig-15. Write Mode
VIH1
RS
VIL1 tSU VIH1 tW VIH1 VIL1 tR tD VOH1 VOL1 VIH1 VIL1 tDH VOH1 VOL1 VIL1 tH tF tH VIH1
R/W
E
DB0~DB7
Valid Data tC
Fig-16. Read Mode

KS0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
tC
CS
VIL1 tSU1 VIH1 VIL1
tR VIH1 VIL1 tSU2
tW tF VIH1 VIL1 tH2
tW
VIL1 tH1 VIH1 VIL1
SCLK
SID
tD tDH VOH1 VOL1
SOD
Fig-17. Serial Interface Mode
Reset Timing (VDD = 2.7 to 5.5V, Ta = -30 to +85) Item Reset low level width (Refer to Fig-18) Symbol tRES Min 10 Typ Max Unit ms
tRES
RESET
VIL1
VIL1
Fig-18. Reset Timing Diagram

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